Лабораторная работа №2
Проверил:
Титов И. И.
Выполнил:
Нижний Новгород
2009 г.
Задание
Построить модель на VHDLи промоделировать в ModelSim делитель частоты с коэффициентом деления 97 с использованием счётчиков типа ИЕ4.
Схема
Описание модели на языке VDHL
-------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-------------------------------------------------------------------
entity CT is
port (R, Inc, CLK: in bit;
EQ0,EQ1,EQ2,EQ3,G9: out bit);
end CT;
-------------------------------------------------------------------
architecture functional of CT is
constant Delay: Time:= 10 ns;
signal Q0,Q1,Q2,Q3:bit;
begin
process(CLK)
begin
if (CLK'event) and (CLK = '0') then
if (R = '1') then
Q0 <= '0' after Delay;
Q1 <= '0' after Delay;
Q2 <= '0' after Delay;
Q3 <= '0' after Delay;
G9 <= '0' after Delay;
else
if (Inc = '1') then
if (Q0 = '0')and(Q1 = '0')and(Q2 = '0')and(Q3 = '0') then
Q0 <= '1' after Delay;
G9 <= '0' after Delay;
else
if(Q0 = '1')and(Q1 = '0')and(Q2 = '0')and(Q3 = '0') then
Q0 <= '0' after Delay;
Q1 <= '1' after Delay;
G9 <= '0' after Delay;
else
if(Q0 = '0')and(Q1 = '1')and(Q2 = '0')and(Q3 = '0') then
Q0 <= '1' after Delay;
G9 <= '0' after Delay;
else
if(Q0 = '1')and(Q1 = '1')and(Q2 = '0')and(Q3 = '0') then
Q0 <= '0' after Delay;
Q1 <= '0' after Delay;
Q2 <= '1' after Delay;
G9 <= '0' after Delay;
else
if(Q0 = '0')and(Q1 = '0')and(Q2 = '1')and(Q3 = '0') then
Q0 <= '1' after Delay;
G9 <= '0' after Delay;
else
if(Q0 = '1')and(Q1 = '0')and(Q2 = '1')and(Q3 = '0') then
Q0 <= '0' after Delay;
Q1 <= '1' after Delay;
G9 <= '0' after Delay;
else
if(Q0 = '0')and(Q1 = '1')and(Q2 = '1')and(Q3 = '0') then
Q0 <= '1' after Delay;
G9 <= '0' after Delay;
else
if(Q0 = '1')and(Q1 = '1')and(Q2 = '1')and(Q3 = '0') then
Q0 <= '0' after Delay;
Q1 <= '0' after Delay;
Q2 <= '0' after Delay;
Q3 <= '1' after Delay;
G9 <= '0' after Delay;
else
if(Q0 = '0')and(Q1 = '0')and(Q2 = '0')and(Q3 = '1') then
Q0 <= '1' after Delay;
G9 <= '0' after Delay;
else
if(Q0 = '1')and(Q1 = '0')and(Q2 = '0')and(Q3 = '1') then
Q0 <= '0' after Delay;
Q1 <= '0' after Delay;
Q2 <= '0' after Delay;
Q3 <= '0' after Delay;
G9 <= '1' after Delay;
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end if;
EQ0 <= Q0;
EQ1 <= Q1;
EQ2 <= Q2;
EQ3 <= Q3;
end process;
end functional;
-------------------------------------------------------------------
entity DC is
port (x0, x1, x2, x3: in Bit;
va: buffer bit_vector(0 to 15));
end DC;
-------------------------------------------------------------------
architecture functional of DC is
constant Delay: Time:= 1 ns;
begin
process(x0, x1, x2, x3)
begin
if (X0 = '0') and (X1 = '0') and (X2 = '0') and (X3 = '0') then
va <= "1000000000000000" after Delay; end if;
if (X0 = '1') and (X1 = '0') and (X2 = '0') and (X3 = '0') then
va <= "0100000000000000" after Delay; end if;
if (X0 = '0') and (X1 = '1') and (X2 = '0') and (X3 = '0') then
va <= "0010000000000000" after Delay; end if;
if (X0 = '1') and (X1 = '1') and (X2 = '0') and (X3 = '0') then
va <= "0001000000000000" after Delay; end if;
if (X0 = '0') and (X1 = '0') and (X2 = '1') and (X3 = '0') then
va <= "0000100000000000" after Delay; end if;
if (X0 = '1') and (X1 = '0') and (X2 = '1') and (X3 = '0') then
va <= "0000010000000000" after Delay; end if;
if (X0 = '0') and (X1 = '1') and (X2 = '1') and (X3 = '0') then
va <= "0000001000000000" after Delay; end if;
if (X0 = '1') and (X1 = '1') and (X2 = '1') and (X3 = '0') then
va <= "0000000100000000" after Delay; end if;
if (X0 = '0') and (X1 = '0') and (X2 = '0') and (X3 = '1') then
va <= "0000000010000000" after Delay; end if;
if (X0 = '1') and (X1 = '0') and (X2 = '0') and (X3 = '1') then
va <= "0000000001000000" after Delay; end if;
if (X0 = '0') and (X1 = '1') and (X2 = '0') and (X3 = '1') then
va <= "0000000000100000" after Delay; end if;
if (X0 = '1') and (X1 = '1') and (X2 = '0') and (X3 = '1') then
va <= "0000000000010000" after Delay; end if;
if (X0 = '0') and (X1 = '0') and (X2 = '1') and (X3 = '1') then
va <= "0000000000001000" after Delay; end if;
if (X0 = '1') and (X1 = '0') and (X2 = '1') and (X3 = '1') then
va <= "0000000000000100" after Delay; end if;
if (X0 = '0') and (X1 = '1') and (X2 = '1') and (X3 = '1') then
va <= "0000000000000010" after Delay; end if;
if (X0 = '1') and (X1 = '1') and (X2 = '1') and (X3 = '1') then
va <= "0000000000000001" after Delay; end if;
end process;
end functional;
-------------------------------------------------------------------
entity and2 is
port (x1, x2: in Bit;
y: out Bit);
end and2;
-------------------------------------------------------------------
architecture functional of and2 is
constant Delay1: Time:= 2 ns;
constant Delay2: Time:= 1 ns;
begin
process(x1, x2)
begin
if (x1 = '0') or (x2 = '0') then y <= '0' after Delay2;
else y <= '1' after Delay1;
end if;
end process;
end functional;
-------------------------------------------------------------------
entity or2 is
port (x1, x2: in Bit;
y: out Bit);
end or2;
-------------------------------------------------------------------
architecture functional of or2 is
constant Delay1: Time:= 2 ns;
constant Delay2: Time:= 1 ns;
begin
process(x1, x2)
begin
if (x1 = '1') or (x2 = '1') then y <= '1' after Delay1;
else y<='0' after Delay2;
end if;
end process;
end functional;
-------------------------------------------------------------------
entity or8 is
port (x1, x2, x3, x4, x5, x6, x7, x8: in Bit;
y: out Bit);
end or8;
-------------------------------------------------------------------
architecture functional of or8 is
constant Delay1: Time:= 2 ns;
constant Delay2: Time:= 1 ns;
begin
process(x1, x2, x3, x4, x5, x6, x7, x8)
begin
if (x1 = '1') or (x2 = '1') or (x3 = '1') or (x4 = '1') or (x5 = '1') or (x6 = '1') or (x7 = '1') or (x8 = '1') then y <= '1' after Delay1;
else y<='0' after Delay2;
end if;
end process;
end functional;
-------------------------------------------------------------------
entity not1 is
port (x: in Bit;
y: out Bit);
end not1;
-------------------------------------------------------------------
architecture functional of not1 is
constant Delay: Time:= 1 ns;
begin
y <= not x after Delay;
end functional;
-------------------------------------------------------------------
entity Circuit is
port (CLK: in Bit;
v: out Bit);
end Circuit;
-------------------------------------------------------------------
architecture structure of Circuit is
component DC is
port (x0, x1, x2, x3: in Bit;
va: buffer bit_vector(0 to 15));
end component;
component CT is
port (R, Inc, CLK: in Bit;
EQ0, EQ1, EQ2, EQ3, G9: out Bit);
end component;
component and2 is
port (x1, x2: in Bit;
y: out Bit);
end component;
component not1 is
port (x: in Bit;
y: out Bit);
end component;
component or2 is
port (x1, x2: in Bit;
y: out Bit);
end component;
signal va0: bit_vector(0 to 15);
signal va1: bit_vector(0 to 15);
signal Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7: Bit;
signal g9,g9_2, r: Bit;
begin
DD1: CT port map (r, '1', CLK, Q0, Q1, Q2, Q3, g9);
DD2: CT port map (r, g9, CLK, Q4, Q5, Q6, Q7, g9_2);
DD3: DC port map (Q0, Q1, Q2, Q3, va0);
DD4: DC port map (Q4, Q5, Q6, Q7, va1);
DD5: and2 port map (va0(7), va1(9), r);
v <= r;
end structure;
-------------------------------------------------------------------
entity Test_Bench is
end Test_Bench;
-------------------------------------------------------------------
architecture Schema of Test_Bench is
component Circuit is
port (CLK: in Bit;
v: out Bit);
end component;
signal CLK: Bit;
signal v: Bit;
begin
process
begin
for i in 0 to 10000 loop
CLK <= '0';
wait for 50 ns;
CLK <= '1';
wait for 50 ns;
end loop;
end process;
Avtomat: Circuit port map(CLK, v);
end Schema;
-------------------------------------------------------------------
4. Результат моделирования.
